CDC 6600

James Thornton, "Considerations in Computer Design - Leading up to the Control Data 6600," CDC brochure BR21, August 1963. James Thornton, "Parallel Operation in the Control Data 6600," Proceedings of the AFIPS FJCC, Part II: Very High Speed Computer Systems, October 1964, pp. 33-40. B.B. Clayton, E.K. Dorff, and R.E. Fagen, "An Operating System and Programming Systems for the 6600," Proceedings of the AFIPS FJCC, Part II: Very High Speed Computer Systems, October 1964, pp. 41-57. This 1964 paper describes SIPROS, which was cancelled. See also R. Wilson, "CDC Scope 3.2," in Studies in Operating Systems, R.M. McKeag, R. Wilson, and D.H.R. Huxtable (eds.), Academic Press, 1976. A brief history of the 6600 operating systems is available in a manual excerpt at bitsavers. Earl Mazorol, Jr., and Maurice Rousch, "Cooling System for Data Processing System," US patent 3,334,684, filed July 8, 1964, published Aug. 8, 1967, assigned to CDC. Seymour Cray and James Thornton, "Multiprocessor Using the Principle of Time-Sharing," US patent 3,337,854, filed July 8, 1964, published Aug. 22, 1967, assigned to CDC. James Thornton and Seymour Cray, "Simultaneous Multiprocessing Computer System," US patent 3,346,851, filed July 8, 1964, published Oct. 10, 1967, assigned to CDC. Seymour Cray of Control Data Corporation awarded Fairchild a development contract for a silicon transistor that switched in less than 3 nanoseconds (ns). Existing silicon transistors offered operation superior to germanium at the elevated ambient temperatures prevalent in large computers but were too slow for Cray's planned new model 6600 supercomputer. Jean Hoerni met CDC's demanding specification by combining gold-doping - the addition of gold impurities (a technique he had developed for use on the company's original product line in 1959) - together with the new epitaxial deposition process. The 2N709 NPN device was introduced in July 1961 as the first silicon transistor to exceed germanium speed. In 1964, CDC placed "one of the largest single orders in the history of the semiconductor industry" with Fairchild for more than 10 million of the devices. See also section IV.F, "A 1960 Supercomputer Design and a Missle Using Silicon Planar Transistors," in C.T. Sah, "Evolution of the MOS Transistor: From Conception to VLSI," Proceedings of the IEEE, 76(10) 1988, pp. 1280-1326. Please see the CDC 6600 section in my history of interrupts page. After the introduction of the 6600, CDC produced a lower cost model 6400 with a sequential CPU and a model 6500 with two sequential processors. The 6500 at LCM is the one used at Purdue University from 1967 to 1989. Most of the models in the Cyber 170-1xx series (ca. 1973) used up to sixteen 16-pin ECL DIP chips instead of discrete transistors within a cordwood logic module so that the same type of frames and cooling could continue to be used. The diagram below is from this CDC training manual on Bitsavers. See pictures of Cyber 170 modules here and here . I believe that this picture from the CDC photograph archives at CBI compares a memory stack from the CDC 6600 with Cyber 170 memory modules. I believe that the description as "logic" is incorrect. See also [this picture that compares several different implementation families.] See chapter 7 of John Vardalas, The Computer Revolution in Canada: Building National Technological Competence, MIT Press, 2001, for a discussion of CDC-Canada's efforts on the Cyber 173. Note: The Cyber 76 was an update of the CDC 7600, and the Cyber 175 and 176 were updates of the Cyber 76. See the 1975 Cyber 170 Systems Hardware Handbook on Bitsavers for more information. pictures and a brief description of the CDC Cyber 205 A68 Gate Array (the description mentions that a larger version of this gate array was used for the ETA-10) contains descriptions of auxiliary board, which seems to match the smaller Cyber 180-860 board at TU Wien and the ECL board at CHM (see pages 5-5 and 5-7 of the manual) LSI