データフロー・アーキテクチャ
Sign in to savecomputer architecture that lack a program counter, in which the executability and execution of instructions is solely determined based on the availability of input arguments to the instructions, with unpredictable execution order
In the Vinony graph
Within Vinony's link graph, データフロー・アーキテクチャ is referenced by 317 other articles, and connects out to central processing unit, CPU cache and hazard.
It sits within the topics Classes of computers, Computer architecture and Hardware acceleration.
Its subject is documented across 12 Wikipedia language editions.
Connections
central processing unit
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CPU cache
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hazard
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computer storage media
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distributed computing
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multiplexer
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system on a chip
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instruction control unit
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general-purpose computing on graphics processing units
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AI accelerator
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Datapath
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No instruction set computing
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neuromorphic computing
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in-memory processing
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Artificial intelligence
Concept
database
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Massachusetts Institute of Technology
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digital object identifier
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compiler
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integrated circuit
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