POWER5
Sign in to savethumb|right|280px|A MCM containing four POWER5 dies and four 36 MB L3 cache dies. Measuring 3.75in x 3.75in thumb|right|280px|Processor module from an IBM i5 system, containing a POWER5+ DCM thumb|2 way POWER5 CPU, heat-sink removed (damaged CPU die) thumb|IBM POWER5+ 8-way MCM CPUs and cache chips. thumb|IBM POWER5+ 8-way MCM Interface. thumb|IBM POWER5+ 8-way MCM side view. The POWER5 is a microprocessor developed and fabricated by IBM. It is an improved version of the POWER4. The principal improvements are support for simultaneous multithreading (SMT) and an on-die memory controller. The PO
Key facts
- CPU.name
- POWER5
- CPU.image
- POWER5-MCM.jpg
- CPU.caption
- POWER5 MCM
- CPU.produced start
- 2004
- CPU.slowest
- 1.5
- CPU.slow unit
- GHz
- CPU.fastest
- 2.3
- CPU.fast unit
- GHz
- CPU.size from
- 130 nm
- CPU.size to
- 90 nm
- CPU.designfirm
- IBM
- CPU.arch
- PowerPC 2.02
- CPU.numcores
- 2
- CPU.l1cache
- 32+32 KB/core
- CPU.l2cache
- 1.875 MB/chip
- CPU.l3cache
- 36 MB/chip (off-chip)
- CPU.predecessor
- POWER4
- CPU.successor
- POWER6
via Wikipedia infobox
Wikidata facts
- Image
- Power5.jpg
Show 1 more fact
- Commons category
- POWER5 microprocessors
Sources (1)
via Wikidata · CC0
~6 min read
Article
8 sectionsContents
- History
- Description
- POWER5+
- Products
- Notes
- See also
- References
- External links
thumb|right|280px|A MCM containing four POWER5 dies and four 36 MB L3 cache dies. Measuring 3.75in x 3.75in thumb|right|280px|Processor module from an IBM i5 system, containing a POWER5+ DCM thumb|2 way POWER5 CPU, heat-sink removed (damaged CPU die) thumb|IBM POWER5+ 8-way MCM CPUs and cache chips. thumb|IBM POWER5+ 8-way MCM Interface. thumb|IBM POWER5+ 8-way MCM side view. The POWER5 is a microprocessor developed and fabricated by IBM. It is an improved version of the POWER4. The principal improvements are support for simultaneous multithreading (SMT) and an on-die memory controller. The POWER5 is a dual-core microprocessor, with each core supporting one physical thread and two logical threads, for a total of two physical threads and four logical threads.
== History ==