SystemVerilog
Sign in to saveSystemVerilog, standardized as IEEE 1800 by the Institute of Electrical and Electronics Engineers (IEEE), is a hardware description and hardware verification language commonly used to model, design, simulate, test and implement electronic systems in the semiconductor and electronic design industry. SystemVerilog is an extension of Verilog.
Key facts
- Programming language.name
- SystemVerilog
- Programming language.logo size
- 240px
- Programming language.file ext
- .sv, .svh
- Programming language.paradigms
- Structured (design)Object-oriented (verification)
- Programming language.designer
- Synopsys, later IEEE
- Programming language.latest release version
- IEEE 1800-2023
- Programming language.typing
- Static, weak
- Programming language.influenced by
- Verilog, VHDL, C++ (design)OpenVera, Java (verification)
via Wikipedia infobox
Wikidata facts
Show 3 more facts
- inception
- 2002-01-01
- file extension
- svr
- issue tracker URL
- accellera.mantishub.io
Sources (3)
via Wikidata · CC0
~25 min read
Article
20 sectionsContents
- History
- Design features
- Data lifetime
- New data types
- Procedural blocks
- Interfaces
- Verification features
- New data types
- Classes
- Constrained random generation
- Randomization methods
- Controlling constraints
- Assertions
- Coverage
- Synchronization
- General improvements to classical Verilog
- Verification and synthesis software
- See also
- References
- External links
SystemVerilog, standardized as IEEE 1800 by the Institute of Electrical and Electronics Engineers (IEEE), is a hardware description and hardware verification language commonly used to model, design, simulate, test and implement electronic systems in the semiconductor and electronic design industry. SystemVerilog is an extension of Verilog.
==History== SystemVerilog started with the donation of the Superlog language to Accellera in 2002 by the startup company Co-Design Automation. The bulk of the verification functionality is based on the OpenVera language donated by Synopsys. In 2005, SystemVerilog was adopted as IEEE Standard 1800-2005. In 2009, the standard was merged with the base Verilog (IEEE 1364-2005) standard, creating IEEE Standard 1800-2009.