Also known as DLX processor, DLX architecture
The DLX (pronounced "Deluxe") is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the Stanford MIPS and the Berkeley RISC designs (respectively), the two benchmark examples of RISC design (named after the Berkeley design).
In the Vinony graph
Vinony's link graph records 30 inbound references to DLX, and connects out to processor register, David A. Patterson and instruction set architecture.
It sits within the topics Instruction set architectures and Soft microprocessors.
Vinony links it to 13 Wikipedia language editions.
Key facts
- CPU architecture.name
- DLX
- CPU architecture.designer
- John L. Hennessy and David A. Patterson
- CPU architecture.bits
- 32-bit
- CPU architecture.introduced
- 1994
- CPU architecture.version
- 1.0
- CPU architecture.design
- RISC
- CPU architecture.type
- Load–store
- CPU architecture.encoding
- Fixed
- CPU architecture.branching
- Condition register
- CPU architecture.endianness
- Bi-endian
- CPU architecture.extensions
- None, but MDMX & MIPS-3D could be used
- CPU architecture.open
- Yes
- CPU architecture.gpr
- 32 (R0=0)
- CPU architecture.fpr
- 32 (paired DP for 32-bit)
via Wikipedia infobox
Wikidata facts
Show 1 more fact
- Stack Exchange tag
- stackoverflow.com/tags/dlx
Sources (1)
via Wikidata · CC0
~5 min read
Encyclopedic overview
6 sectionsContents
- History
- Instruction decoding
- Pipeline
- See also
- References
- External links
The DLX (pronounced "Deluxe") is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the Stanford MIPS and the Berkeley RISC designs (respectively), the two benchmark examples of RISC design (named after the Berkeley design).
The DLX is essentially a cleaned up (and modernized) simplified Stanford MIPS CPU. The DLX has a simple 32-bit load/store architecture, somewhat unlike the modern MIPS architecture CPU. As the DLX was intended primarily for teaching purposes, the DLX design is widely used in university-level computer architecture courses.
Excerpted from Wikipedia’s “DLX” article, available under the CC BY-SA 4.0 licence.