OpenRISC
Sign in to saveOpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computer (RISC) principles. It includes an instruction set architecture (ISA) using an open-source license. It is the original flagship project of the OpenCores community.
Key facts
- CPU architecture.name
- OpenRISC
- CPU architecture.designer
- Originally Damjan Lampret, now the OpenRISC Community (Stafford Horne etc.)
- CPU architecture.bits
- 32-bit, 64-bit
- CPU architecture.version
- 1.4
- CPU architecture.design
- RISC
- CPU architecture.encoding
- Fixed
- CPU architecture.endianness
- Big; unimplemented stub for Little
- CPU architecture.page size
- 8 KiB
- CPU architecture.extensions
- ORFPX32/64, ORVDX64
- CPU architecture.open
- Yes (LGPL / GPL), hence royalty free
- CPU architecture.gpr
- 16 or 32
- CPU architecture.fpr
- Optional
via Wikipedia infobox
Wikidata facts
- Official website
- openrisc.io
Show 1 more fact
- inception
- 2000-00-00
Sources (1)
via Wikidata · CC0
~7 min read
Article
12 sectionsContents
- Instruction set
- Implementations
- Commercial implementations
- Academic and non-commercial use
- Toolchain support
- Operating system support
- Linux support
- RTOS support
- QEMU support
- See also
- References
- External links
OpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computer (RISC) principles. It includes an instruction set architecture (ISA) using an open-source license. It is the original flagship project of the OpenCores community.
The first (and only) architectural description is for the OpenRISC 1000 ("OR1k"), describing a family of 32-bit and 64-bit processors with optional floating-point arithmetic and vector processing support. The OpenRISC 1200 implementation of this specification was designed by Damjan Lampret in 2000, written in the Verilog hardware description language (HDL). The later mor1kx implementation, which has some advantages compared to the OR 1200, was designed by Julius Baxter and is also written in Verilog. Software simulators also exist which implement the OR1k specification.