Clock gating
Sign in to savetechnique used in synchronous circuits for reducing dynamic power dissipation, by adding more logic to a circuit to prune the clock tree (disabling portions of the circuitry so that the flip-flops in them do not have to switch states)
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- Gated clk1.png
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- Clock gating
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via Wikidata · CC0
Article · Italiano
Il clock gating è una tecnica di progettazione dei circuiti integrati che permette di ridurre il consumo di potenza dei chip.
Abstract from DBpedia / Wikipedia · CC BY-SA